1. Field
The present invention relates generally to data communications, and in particular serial point-to-point data communications.
2. Background Art
The speed of computers has dramatically increased over recent years. A considerable portion of that increase has resulted from the increased CPU speeds. However, computer speed also depends upon the speed of data communications, i.e., the ability for CPUs to communicate data to and from peripheral devices. For some time, the peripheral component interconnect (PCI) bus provided adequate peripheral connectivity. However, with increased CPU speeds and greater data transfer demands, the PCI bus quickly became the slowest link between CPU and peripheral. In particular, the PCI bus imposed substantial pin, power and clocking disadvantages in order to meet the increased data transfer requirements.
In response to these disadvantages, the PCI Express industry standard developed. The PCI Express industry standard adopted a serial protocol that uses low voltage differential signals, does not impose the same clocking disadvantages, and delivers higher bandwidth with reduced pin count. PCI Express offers up to 32 data channels (known as lanes) that provide serial point-to-point connectivity between a “root” device and an “endpoint” device.
The PCI Express protocol is a layered protocol, with the layers including a transaction layer, a data link layer, and a physical layer. The fundamental building block of communication between PCI Express-compliant devices is the transaction layer packet (TLP). The TLP contains a header, a data payload and an error correction segment (called a digest). One or more TLPs create a transaction that enables an operation in a PCI Express-complaint device. For example TLP transactions facilitate memory read and write operations.
As noted above, the PCI Express protocol was developed to offer a flexible high speed approach to the modern data communication device-to-device challenges. Nevertheless, with the ever increasing demand for efficient data transfer to service high performance computer designs, the efficiency of data transfer remains a high priority. Thus, there is an on-going need for enhancements to the PCI Express protocol. Any improvements to the PCI Express protocol must necessarily be backwards compatible with the standard PCI Express specifications.
Therefore, there is a need for a method and system to increase the efficiency of the standard PCI Express transactions while remaining compatible with the standard PCI Express specifications. In particular, since the PCI Express headers contribute to transfer inefficiency, there is a need to focus on PCI headers to reduce the inefficiency.